The present invention is related to delay lines, and more particularly to a system and method for controlling the amount of delay over a range of delays and operating conditions.
Delay lines serve a variety of functions within digital systems. They can be used, for instance, to deskew a clock or to change the phase of a clock or of a signal.
To date, a variety of approaches have been used to add delay to a signal. Delay has been implemented using delay lines external to the integrated circuit. Such an approach, however, consumes pins and real estate both on the integrated circuit and on the circuit board.
Conventional Delay Locked Loops (DLLs) have also been used. DLLs, however, limit flexibility. That is, only a limited number of delay choices can be provided and at a rather coarse granularity. Furthermore, the choices must be determined at design time.
Discrete delay lines have also been implemented directly on the integrated circuit. Under such an approach, standard cell or other ASIC technology is used to implement the delay line. The integrated circuit approach to discrete delay lines is advantageous in that regular ASIC design and verification tools can be used to design and test the delay line. Delay lines designed using this approach, however, can exhibit variation in delay as the operating environment (e.g., temperature, voltage level, etc.) changes. In addition, since the delay line is implemented directly on an integrated circuit, it can exhibit changes in delay due to variations in the integrated circuit manufacturing process.
Delay within a discrete delay line varies with environmental factors such as temperature, voltage and process. In the past, maintaining a consistent delay across temperature and voltage has been difficult. DLLs avoid this problem but at the cost described above.
What is needed is a discrete delay line control system and method that uses regular ASIC design and verification tools but which can be controlled to limit variations due to process, temperature, voltage level and other operating parameters. In addition, what is needed is a delay control process that is capable of managing discrete delay lines with a wide delay range and which is capable of automatically obtaining any delay value within the delay line range. Finally, what is needed is a method of controlling a delay line which can measure and adjust delay accurately, and continue to monitor performance after the initial setting.
According to one aspect of the present invention, a system and method of controlling delay in a delay line is described. In a delay line having a system mode and an oscillator mode, wherein the delay line delays a signal as a function of a delay code, the method comprises setting the delay code, placing the delay line in oscillator mode, determining frequency of oscillation of the delay line, comparing the frequency of oscillation to a target frequency and adjusting the delay code until the frequency of oscillation of the delay line is substantially equal to the target frequency.
According to another aspect of the present invention, a system and method of controlling delay in a signal delay line having an input and an output is described. The signal delay line delays signals as a function of a delay code. A replicate delay line having an input and an output is provided, wherein the replicate delay line delays signals as a function of a delay code. The output of the signal delay line is fed back to its input to form an oscillator having an oscillation frequency. The oscillation frequency of the signal delay line is determined and compared to a target frequency. The delay code of the signal delay line is then adjusted until the frequency of oscillation of the signal delay line is substantially equal to the target frequency. The replicate delay line is driven with the delay code of the signal delay line and the output of the replicate delay line is fed back to its input to form an oscillator having an oscillation frequency. The oscillation frequency of the replicate delay line is determined and the delay code of the replicate and signal delay lines is adjusted as a function of changes in the oscillation frequency of the replicate delay line.
According to yet another aspect of the present invention, a delay line includes a master delay line, a slave delay line, and a delay line controller connected to the master delay line and the slave delay line. The master delay line sets delay as a function of a delay code. In addition, the master delay line includes an oscillator mode having an oscillation frequency which is a function of delay in the master delay line. The slave delay line sets delay as a function of a delay code. In addition, the slave delay line includes an oscillator mode having an oscillation frequency which is a function of delay in the slave delay line. The delay line controller includes a frequency counter and a state machine, wherein the frequency counter determines the oscillation frequencies of the master and slave delay lines when the master and slave delay lines are in oscillator mode and wherein the state machine adjusts the delay code to both the master and slave delay lines as a function of the oscillation frequencies of the master and slave delay lines.